Field
The present disclosure relates generally to a layout construction, and more particularly, to a via structure for optimizing signal porosity.
Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as a system-on-a-chip (SoC) device, may contain thousands to millions of standard cells. Reducing a size/area footprint of ASICs is beneficial. Improving a signal porosity/routability may allow for the size/area footprint of ASICs to be reduced. Accordingly, there is a need for improving signal porosity/routability.